3D modeling of dual-gate FinFET

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dc.contributor.authorMil’shtein, Samson
dc.contributor.authorDevarakonda, L.
dc.contributor.authorZanchi, B.
dc.contributor.authorPalma, J.
dc.date.accessioned2015-05-15T14:50:45Z
dc.date.accessioned2020-02-10T21:21:49Z
dc.date.available2015-05-15T14:50:45Z
dc.date.available2020-02-10T21:21:49Z
dc.date.issued2012
dc.descriptionSamson Mil’shtein is a professor in the Electrical and Computer Engineering Department as well as the Director of the Advanced Electronic Technology Center at UMass Lowellen_US
dc.description.abstractThe tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 > Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.en_US
dc.identifier.citationMil’shtein, Samson, et al (2012). 3D modeling of dual-gate FinFET. Nanoscale Research Letters, 7(625), 1-5. Available at: http://www.nanoscalereslett.com/content/7/1/625en_US
dc.identifier.otherdoi:10.1186/1556-276X-7-625
dc.identifier.urihttp://hdl.handle.net/20.500.12517/93
dc.language.isoen_USen_US
dc.publisherNanoscale Research Lettersen_US
dc.relation.ispartofseriesInternational Conference on Superlattices, Nanostructures, and Nanodevices;ICSNN 2012
dc.title3D modeling of dual-gate FinFETen_US
dc.typeArticleen_US

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